1. Field of the Invention
The present invention relates to a semiconductor device, a method of manufacturing the semiconductor device, and a solid-state imaging apparatus. Specifically, the present invention relates to a semiconductor device including a transistor formed with a silicide layer, a method of manufacturing the semiconductor device, and a solid-state imaging apparatus.
2. Description of the Related Art
Typical solid-state imaging devices which convert image light as an image signal to an electrical signal include a CCD image sensor and a MOS image sensor.
In the MOS image sensor, an imaging region including a light receiving unit (photodiode) which generates electrical charge with light radiation and a peripheral circuit region which reads the electrical charge generated in the imaging region as an electrical signal (voltage signal in most cases) are provided on a common substrate. Herein, a pixel transistor (MOS transistor) is formed in the imaging region, and a peripheral transistor (MOS transistor) is formed in the peripheral circuit region.
Along with a further increase in drive speed of solid-state imaging devices in recent years, it is desirable that a peripheral transistor also be driven at high speed. In order to improve the operation speed of a peripheral transistor to meet such demand, patent documents such as International Publication No. 03/096421 disclose a technique for forming a silicide layer, which is a compound of a refractory metal such as Ti or Co and Si, on each surface of a gate electrode, a source region, and a drain region of the peripheral transistor.
A silicide layer is formed by forming a layer of a refractory metal on the surface of a source region or a drain region and reacting silicon and the refractory metal. However, incomplete reaction of the silicon and the refractory metal and diffusion of the unreacted refractory metal which occurs with some probability can cause metal contamination such as a white spot.
Therefore, a configuration is preferable in which a silicide layer is not formed in an imaging region. That is, a configuration is preferable in which a silicide layer is formed in a transistor provided in a peripheral circuit region and a silicide layer is not formed in a transistor provided in an imaging region.
As one example of a method of forming a silicide layer only in a transistor in a peripheral circuit region, it is conceivable to form a blocking layer which prevents a refractory metal from contacting a silicon substrate only in the imaging region in addition to a sidewall.
Specifically, as shown in FIG. 17A, a gate electrode 101 is formed on a silicon substrate 100 with a gate insulating layer (not shown) in between, an oxide layer 102 is formed as a layer on top of the gate electrode 101, and a nitride layer 103 is further formed as a layer on top of the oxide layer 102. Note that a sidewall is formed by an etch-back process on the oxide layer 102 and the nitride layer 103. By forming a nitride layer 105 which functions as a blocking layer only in an imaging region 104 for a transistor configured in this manner, a silicide layer can be formed only in a transistor in a peripheral circuit region 106.
As another example of the method of forming a silicide layer only in a transistor in a peripheral circuit region, it is conceivable to form a blocking layer which prevents a refractory metal from contacting a silicon substrate in an imaging region as a part of a layer forming a sidewall.
Specifically, as shown in FIG. 17B, the gate electrode 101 is formed on the silicon substrate 100 with a gate insulating layer (not shown) in between, and the nitride layer 105 which functions as a blocking layer is formed as a layer on top of the gate electrode 101. Further, the nitride layer 103 is formed as a layer on top of the nitride layer 105. Note that a sidewall is formed by an etch-back process on the nitride layer 105 and the nitride layer 103, and that the nitride layer 105 and the nitride layer 103 are removed from a source region and a drain region of a transistor in the peripheral circuit region 106.
Since only the surface of the source region and the drain region of the transistor in the peripheral circuit region 106 of the silicon substrate 100 is exposed, a silicide layer can be formed only in the transistor in the peripheral circuit region 106.